MAX8896EREE+T【PDF 10/17 页】IC REG TRPL BCK/LINEAR 16UCSP

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Sheet目录44

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Dual PWM Step-Down Converter in a 2mm x

2mm Package for WCDMA PA and RF Power

10 ______________________________________________________________________________________

Pin Description

NAME

FUNCTION

REFBP

Reference Noise Bypass. Bypass REFBP to AGND with a 0.033礔 ceramic capacitor to reduce noise

on the LDO output. REFBP is internally pulled down through a 1k& resistor during shutdown.

AGND

Low-Noise Analog Ground. Connect AGND to the ground plane at a single point away from high

switching currents. See the PCB Layout section.

REFIN

DAC-Controlled Input. The output of the PA step-down converter is regulated to 2.5 x V

REFIN

. When

REFIN

reaches 0.396 x V

, bypass mode is enabled.

PGND1

Power Ground for OUT1. Connect PGND1 to the ground plane near the input and output capacitor

grounds. See the PCB Layout section.

LDO

200mA LDO Regulator Output. Bypass LDO with a 1礔 ceramic capacitor as close as possible to

LDO and ground. Leave LDO unconnected if not used.

PAEN

OUT1 Enable Input. Connect PAEN to IN1 or logic-high for normal operation. Connect to ground or

logic-low to shut down OUT1. Internally connected to ground through an 800k& resistor.

RFEN2

OUT2 and LDO Enable Input. Connect RFEN1 or RFEN2 to IN2 or logic-high for normal operation.

Connect RFEN1 and RFEN2 to ground or logic-low to shut down OUT2 and the LDO. Internally

connected to ground through an 800k& resistor.

LX1 Inductor Connection. Connect an inductor from LX1 to the output of OUT1.

OUT2

Output of OUT2. OUT2 is also the supply voltage input for the LDO. Bypass OUT2 with a 2.2礔

ceramic capacitor as close as possible to OUT2 and PGND2.

RFEN1

OUT2 and LDO Enable Input. Connect RFEN1 or RFEN2 to IN2 or logic-high for normal operation.

Connect RFEN1 and RFEN2 to ground or logic-low to shut down OUT2 and the LDO. Internally

connected to ground through an 800k& resistor.

Supply Voltage Input for Internal Reference and Control Circuitry. Connect V

to a battery or supply

voltage from 2.7V to 5.5V. Bypass V

with a 0.1礔 ceramic capacitor as close as possible to V

and AGND. Connect V

, IN1, and IN2 to the same source.

IN1

Supply Voltage Input for OUT1. Connect IN1 to a battery or supply voltage from 2.7V to 5.5V. Bypass

IN1 with a 4.7礔 ceramic capacitor as close as possible to IN1 and PGND1. Connect IN1, V

CC,

and

IN2 to the same source.

PGND2

Power Ground for OUT2. Connect PGND2 to the ground plane near the input and output capacitor

grounds. See the PCB Layout section.

LX2 Inductor Connection. Connect an inductor from LX2 to the output of OUT2.

IN2

Supply Voltage Input for OUT2. Connect IN2 to a battery or supply voltage from 2.7V to 5.5V. Bypass

IN2 with a 2.2礔 ceramic capacitor as close as possible to IN2 and PGND2. Connect IN2, V

and

IN1 to the same source.

PAOUT

PA Connection for Bypass Mode. Internally connected to IN1 using the internal bypass MOSFET

during bypass mode. PAOUT is internally connected to the feedback network for OUT1. Bypass

PAOUT with a 4.7礔 ceramic capacitor as close as possible to PAOUT and PGND1.

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